The first hour on a dense board is usually escape work, not the rest of the routing. The chip is a ball grid array, a BGA, a package whose solder balls sit in a grid on the underside. Once the part is down, you cannot see them. Fanout is the short path from each ball out to a via and a trace, so the rest of the board can connect. A via is a plated hole that joins copper on one layer to copper on another. Until July 8, 2026, Quilter's customers drew that escape by hand in an ECAD tool. ECAD means the electronics CAD program. Quilter says it reads Altium, KiCad, Cadence, and Xpedition.
That day, Quilter said it generates the fanout while it builds layout candidates. A candidate is one full board the system proposes. Coverage, the press release says, includes standard-pitch, dense, and irregular ball patterns, and the feature is beta. Quilter calls the product physics-driven layout automation, available as a cloud platform or an on-premise deployment. The release lists no price. I will not invent one.
What actually changed?
Read the press release and the changelog as a pair. On May 1, 2026, the changelog limited fanout to square ball patterns and told you to choose "Generate Fanout" on the Comprehensions page. The July 8 press release widens that to standard-pitch, dense, and irregular patterns, still beta. I would treat July 8 as the current claim, and keep May 1 in mind when a connector footprint is not a square grid.
A hand fanout freezes escapes the tool then has to route around. Quilter says it picks the via pattern, the direction, and the breakout traces from the placement, the stackup, and the other routing. A stackup is the ordered pile of copper and insulator, with thickness and material. Get that pile wrong and every later electrical number is fiction.
The same note lists the rest of the 2026 work, and two items that are not shipped. Projects group the iterations of one design. Calculated impedance uses the Simbeor solver from Simberian, and you can override those numbers. You can name which ground net is poured on each ground layer. Setup shows stackup layers, materials, and fabricator limits before you submit. A proximity rule can hold one part within a set distance of a pin on another. Blind and buried vias are in development, not in this release. A blind via starts outside and stops partway. A buried via joins only inner layers. Quilter routes through-vias today, holes that go through the whole board. Full clearance import is also still "in development" on July 8, even though May 1 described a silent early beta for Altium. I would run my own check after export.
How does the new piece work?
I would not call Quilter an autorouter with a new button on it. The company's June 3, 2026 essay, "The PCB Autorouter Was the Right Idea," draws the line. A traditional autorouter treats placement as finished. It tries to connect the nets, each net being the pins that must share a connection, inside the design rules. The old score was completion. A board can pass that test and still misbehave.
Quilter says it explores many whole-board candidates with reinforcement learning, a training style that tries layouts and keeps the choices that score better. While it builds a candidate, it checks electrical intent. Impedance is the opposition a fast signal sees on a trace, in ohms, set by width, spacing, and the materials around it. A return path is the copper the return current follows, usually the ground under the trace. A differential pair is two traces that carry one signal as opposite swings, the way USB does. Differential coupling is how hard those traces push on each other. Quilter says it watches impedance, return path, and that coupling while it builds the board. A geometry check still matters. It is not the only check.
A DRC, a design-rule check, is that geometry test: spacing, width, and the fabricator's limits. The June 3 essay calls the electrical tests Physics Rule Checks, and says they are not a compliance certificate. HDI, high-density interconnect, is the limit this release does not cross. Those boards escape tight balls with tiny blind and buried vias. A through-via is wider than the trace it serves. If the balls are packed tighter than that hole, this beta will not invent a smaller one.
What does this look like on a real project?
Say the board is a small robot controller. The processor is a BGA. A current-sense resistor has to sit near one pin of the power chip. A USB pair has an impedance target. Two grounds share the board. The old sequence was hand fanout, hand placement for the sense resistor, and a separate impedance calculator.
Quilter's path is to upload a schematic and a board outline, check the stackup on the setup screens, name both grounds, and let fanout run with the rest of the candidate. The sense resistor uses the May 1 proximity rule: child part, parent part, pin, and a maximum distance. For the USB pair, June 30 stopped forcing differential impedance to twice the single-ended number. The changelog's example is 50 ohms single-ended beside 90 ohms differential. Projects, from April 7, keep the jobs together. Quilter says customers usually iterate two to four times, and a new upload should stay within 10 percent of the original bill of materials, the parts list. I would still open the winner in my ECAD and run that tool's DRC. I have not run this July 8 build.
How does it compare with the previous version?
Before May, a dense board reached Quilter only after a person had fanned the BGA out. May 1 removed that prep for square patterns. July 8 widens the patterns and still says beta. The press release does not claim an HDI product.
The press release says earlier versions guessed at inputs such as which ground to pour. Fanout is the headline because customers still drew it by hand before submit. June 30 also added a beta Floorplan page and Cadence schematic import. Quilter says several smarter behaviors need the schematic.
Where does it sit next to other tools a maker already uses?
Quilter does not replace Altium, KiCad, Cadence, or Xpedition. It reads those files and, the company says, writes a candidate back in the native format. The autorouter inside those tools freezes placement and scores completion. Quilter's June 3 essay says Quilter searches placement and routing together. I would keep the ECAD program for review, fabrication files, and the last fixes.
Simbeor is inside the impedance math. Your fabricator's stackup note is still the source of truth. The July 8 release says cloud or on-premise. The June 3 essay adds that the hosted service runs on Amazon's cloud, and that a design which cannot leave your network can run in your own Amazon, Microsoft, or Google cloud account.
What does this cost, and who can use it today?
The July 8 release prints no price. Ask Quilter before a number goes in a budget. It does state cloud or on-premise access, and files from Altium, KiCad, Cadence, and Xpedition. Fanout is beta. Blind and buried vias are unavailable. Through-vias are what it routes today. I would not treat clearance import as finished.
What is still unproven?
Irregular balls are where I would look first, because May 1 published the square case and July 8 is the expansion. Compare one trusted hand fanout with one generated candidate. If the escape blocks a pair or cuts the ground under a fast trace, the hour you saved was not real.
The June 3 essay still had length matching and RF in development, and a sweet spot of about 100 to 1,000 parts, pin density under 20 percent, signals to about 10 GHz, and through-hole vias. July 8 does not ship length matching or RF. Physics checks are not a compliance lab. Sergiy Nesterenko, the founder, said, "How much of a layout an engineer hands to Quilter is the engineer's call." I would hand over a through-via BGA whose pitch has room, and keep HDI, RF, and the final sign-off.
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Sources and image credits
- Quilter announcement (www.quilter.ai)
- Images: published by Quilter with the announcement.
